Digi NS9750 - Manual (Page 488)

C a r d B u s S u p p o r t
4 6 4 N S 9 7 5 0 H a r d w a r e R e f e r e n c e
Notes:
BOOTSTRAP[1]
and
PCI_CENTRAL_RSC_n
are two strapping pins that must be
pulled low to configure the IO and internal arbiter for CardBus. Because
CardBus does not have an
IDSEL
signal, it is pulled high. As a result, NS9750
captures any configuration accesses from the external CardBus device since
it is the only other device on the bus.
The internal arbiter must be used for CardBus applications. Requests to the
arbiter from the
REQ2#
and
REQ3#
pins, however, must be disabled by
clearing the
PCIEN_M2
and
PCIEN_M3
bits in the PCI Arbiter Configuration
register. The arbiter parks the bus only on the bridge — not on the last
granted master, as is done for PC I.
CardBus adapter requirements
In a CardBus application, NS9750 is the adapter, or bridge. The adapter is required to
have a set of socket registers that provide socket control and status. The following
NS9750 registers support this requirement:
REQ2# CCD1 Input Card detect pin. Pulled up by system when socket is
empty and pulled low when the external CardBus
device is present in the socket.
REQ3# CCD2 Input Card detect pin. Pulled up by system when socket is
empty and pulled low when the external CardBus
device is present in the socket.
N/A CVS1_DET Input Voltage sense detect pin. Can be any GPIO input.
Used to detect whether the external CardBus device
shorts CVS1 to ground.
N/A CVS2_DET Input Voltage sense detect pin. Can be any GPIO input.
Used to detect whether the external device shorts
CVS2 to ground.
N/A CPWR[3:0] Output Controls to the external power controller that may be
providing the power to the CardBus socket. Required
only for hot-insertion and hot-removal. Can be any
GPIO outputs.
PCI Signal
CardBus
Signal
CardBus type Comments
Table 285: CardBus IO muxing