Digi NS9750 - Manual (Page 20)

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SPI master mode 0 and 1: 2-byte transfer ..................................829
SPI master mode 2 and 3: 2-byte transfer ..................................829
SPI slave mode 0 and 1: 2-byte transfer ....................................830
SPI slave mode 2 and 3: 2-byte transfer ....................................830
IEEE 1284 timing .......................................................................831
IEEE 1284 timing example .....................................................831
USB timing ..............................................................................832
USB differential data timing ..................................................833
USB full speed load timing ....................................................833
USB low speed load.............................................................834
Reset and hardware strapping timing ..............................................835
JTAG timing ............................................................................836
Clock timing ............................................................................837
USB crystal/external oscillator timing ......................................837
LCD input clock timing .........................................................838
System PLL bypass mode timing..............................................839
C h a p t e r 1 8 : P a c k a g i n g ...................................................................................................841
Product specifications .........................................................845