C registers – Digi NS9750 User Manual

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I 2 C M a s t e r / S l a v e I n t e r f a c e

Bus arbitration

Any

M_READ

M_WRITE

command causes the I

C module to participate in the bus

arbitration process when the I

C bus is free (idle). If the module becomes the new

bus owner, the transaction goes through. If the module loses bus arbitration, an

M_ARBIT_LOST

interrupt is generated to the host processor and the command must be

reissued.

C registers

All registers have 8-bit definitions, but must be accessed in pairs. For example,

TX_DATA_REG

and

CMD_REG

are written simultaneously and

RX_DATA_REG

and

STATUS_REG

are read simultaneously.

Table 336 shows the register addresses.

After a reset, all registers are set to the initial value. If an unspecified register or bit
is read, a zero is returned.

Register

Description

9050 0000

Command Transmit Data register (

CMD_TX_DATA_REG

)

Status Receive Data register (

STATUS_RX_DATA_REG

)

9050 0004

Master Address register

9050 0008

Slave Address register

9050 000C

Configuration register

Table 336: I

C register address map