Digi NS9750 User Manual
Page 365
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E t h e r n e t C o m m u n i c a t i o n M o d u l e
D19
R/W
ERXINIT
0
Enable initialization of RX buffer descriptors
0
Do not initialize
1
Initialize
When set, causes the
RX_RD
logic to initialize the internal
buffer descriptor registers for each of the four pools from
the buffer descriptors pointed to by RXAPTR, RXBPTR,
RXCPTR, and RXDPTR. This is done as part of the RX
initialization process. RXINIT is set in the Ethernet
General Status register (see page 344) when the
initialization process is complete, and ERXINIT must be
cleared before enabling frame reception from the MAC.
The delay from ERXINIT set to RXINIT set is less than
five microseconds.
D18:16
N/A
Reserved
N/A
N/A
D15:14
R/W
PHY_MODE
00
Ethernet interface mode
00
10/100 Mbit MII mode
01
10/100 Mbit RMII mode
10
Reserved
11
Reserved
Identifies what type of Ethernet PHY is attached to
NS9750. NS9750 supports two styles of Ethernet PHY:
MII and RMII.
This field should be changed only while the MAC is reset.
D13
N/A
Reserved
N/A
N/A
D12:11
R/W
Not used
0
Always write as 0.
D10
R/W
RXALIGN
0
Align RX data
0
Standard receive format. The data block immediately
follows the 14-byte header block.
1
The receiver inserts a 2-byte padding between the 14-
byte header and the data block, causing longword
alignment for both the header and data blocks.
D09
R/W
MAC_HRST
1
MAC host interface soft reset
0
Restore MAC, STAT, SAL, RX_WR, and TX_RD to
normal operation.
1
Reset MAC, STAT, programmable registers in SAL,
RX_WR, and TX_RD. Keep high for minimum of
5
μsec to guarantee that all functions get reset.
Bits
Access
Mnemonic
Reset
Description
Table 206: Ethernet General Control Register #1