Digi NS9750 - Manual (Page 760)

U S B h o s t b l o c k r e g i s t e r s
7 3 6 N S 9 7 5 0 H a r d w a r e R e f e r e n c e
Register bit assignment
Bits Access Mnemonic Reset Description
D31 R/W MIE 0b Master interrupt enable
0 Ignored by the host controller
1 Enables interrupt generation due to events specified
in the other bits of this register.
D30 R/W OC 0b Ownership change
0 Ignore
1 Enable interrupt generation due to ownership change.
D29:07 N/A Reserved N/A N/A
D06 R/W RHSC 0b Root hub status change
0 Ignore
1 Enable interrupt generation due to root hub status
change.
D05 R/W FNO 0b Frame number overflow
0 Ignore
1 Enable interrupt generation due to frame number
overflow.
D04 R/W UE 0b Unrecoverable error
0 Ignore
1 Enable interrupt generation due to unrecoverable
error.
D03 R/W RD 0b Resume detect
0 Ignore
1 Enable interrupt generation due to resume detect.
Table 427: HcInterruptEnable register
13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 30
RD SF WDH SO
MIE OC Reserved
Reserved RHSC FNO UE