Digi NS9750 - Manual (Page 714)

B B u s s l a v e a n d D M A i n t e r f a c e
6 9 0 N S 9 7 5 0 H a r d w a r e R e f e r e n c e
Register bit assignment
Forward Data DMA Control register
Address: 9040 0028
The Forward Data DMA Control register controls when the forward data DMA buffer is
closed, using two components:
16-bit maximum buffer counter. The maximum buffer counter increments
each time a DMA transfer occurs, by the number of bytes in the transfer.
The counter is reset each time a DMA completes. If the counter reaches or
exceeds the forward data maximum buffer size (FwDatMaxBufSize), the
1284 module signals the DMA channel to close the buffer and start a new
one. A (maskable) interrupt is generated when FwDatMaxBufSize is reached.
Future bytes are moved using DMA when the next DMA is initiated by the
DMA controller.
Note: This counter should not be set to a value greater than the buffer
length field value set in the 1284 forward data DMA channel descriptor.
16-bit byte gap counter. The byte gap counter increments on each clock
cycle when a byte is not read from the host, with a maximum programmable
interval of 1.3 ms based on a 50 MHz BBus clock. The counter is reset when
a byte is read from the host. If the counter reaches the forward data byte
gap timeout (FwDatByteGapTimer), the following occurs:
a
Where the FIFOs are written with dwords containing four bytes each,
the gap timeout forces an incomplete dword (that is, 1–3 bytes) to be
written to the FIFO.
Bits Access Mnemonic Reset Description
D31:16 R/W FwCmdMaxBufSize 0x0 Forward command maximum buffer size
Maximum buffer size in bytes.
D15:00 R/W FwCmdByteGapTimer 0x0 Forward command byte gap timeout
16-bit byte gap timer in BBus clock cycles.
Table 397: Forward Command DMA Control register