Register bit assignment examples, Domain – Digi NS9750 User Manual
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M e m o r y C o n t r o l l e r
Register bit assignment
Examples
Generic formula: DynamicRefresh = (((t
REF
/ #rows) * speed grade) / 32)
For 4k rows:
Refresh period = 64
μ
s
Speed grade = 200 MHz
Calculation = ((64e
-3
/ 4096) * 200e
+6
) / 32 = 97 = 0x61
For 8k rows:
Refresh period = 64
μ
s
Speed grade = 150 MHz
Calculation = ((64e
-3
/ 8192) * 150e
+6
) / 32 = 36 = 0x24
Notes:
The refresh cycles are evenly distributed. There might be slight variations,
however, when the auto-refresh command is issued, depending on the
status of the memory controller.
Unlike other SDRAM memory timing parameters, the refresh period is
programmed in the
HCLK
domain.
Bits
Access
Mnemonic
Description
D31:11
N/A
Reserved
N/A (do not modify)
D10:0
R/W
REFRESH
Refresh timer
0x0
Refresh disabled (reset value on
reset_n
)
0x1–0x77F n(x16)
16n
HCLK
ticks between SDRAM refresh cycles
Table 142: Dynamic Memory Refresh Timer register
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
30
Reserved
REFRESH
Reserved