Digi NS9750 - Manual (Page 884)

I n d e x - 14
Static Memory Turn Round Delay 0-3
registers
239
static memory write control 136 - 143
Static Memory Write Delay 0-3
registers 238
Static Memory Write Enable Delay 0-3
registers 234
Status register 207
system overview 117
write protection
dynamic memory controller 162
static memory controller
122
Memory Management Unit. See MMU.
memory map 118
memory mapped peripherals 123
memory timing 795 - 812
MII
315
MII Management Address register
361
MII Management Command register 360
MII Management Configuration
register 359
clocks field settings
360
MII Management Indicators register
363
MII Management Read Data register 363
MII Management Write Data register 362
Miscellaneous System Configuration and
Status register
296
MMU
78
-
105
access permissions and domains 79
address translation 81 - 95
coarse page table descriptor 87
disabling 104
domain access control
98
enabling 103
external aborts 102
fault checking sequence 99
alignment faults 101
domain faults
101
permission faults 102
translation faults
101
features
78
fine page table descriptor 88
first-level descriptor 84
first-level fetch 84
MMU faults and aborts 95 - 98
program accessible registers
80
second-level descriptor 89
section descriptor 86
subpages 95
TLB structure 104
translated entries
79
translating large page references
91
translating section references 89
translating small page references 93
translating tiny page references 94
translation table base 82
N
negotiation, IEEE 1284
676
next base address update interrupt
(LNBU) 599
nibble mode 672
data transfer cycle
672
Non Back-to-Back Inter-Packet-Gap
register 355
noncacheable instruction fetches 111
AHB behavior 112
NS9750
17
10/100 Ethernet MAC
3
1284 parallel peripheral port 5
clock generation/system pins
pinout 26
clock generator
7
configuring for CardBus support
463
definition 1 , 2