Pci arbiter interrupt status register, Register bit assignment, Table 261: pci arbiter interrupt status register – Digi NS9750 User Manual
Page 448: Table 260: pci arbiter configuration register
P C I b u s a r b i t e r
4 2 4
N S 9 7 5 0 H a r d w a r e R e f e r e n c e
PCI Arbiter Interrupt Status register
Address: A030 0004
The PCI Arbiter Interrupt Status register reports broken masters (that is, masters that
do not respond in 16 clocks after being granted the bus) and PCI system errors from
external PCI agents (that is,
SERR#
asserted for 1 clock cycle). There is a separate bit
for each of the interrupt sources, and each bit can cause an interrupt if the
associated bit in the PCI Arbiter Interrupt Enable register is set to 1.
Note:
For diagnostics, software can cause an interrupt by writing a 1 to a bit
that is set to 0. Otherwise, in normal operation, the software writes a 1 to
a bit that is set to clear the bit and the interrupt from the PCI arbiter.
Register bit assignment
D00
R
PCI_CTL_RSC_n
N/A
PCI_CENTRAL_RSC_n input to NS9750
(NS9750 has internal pulldown)
0
NS9750 provides PCI central resource functions
(pulldown)
1
NS9750 does not provide PCI central resource
functions
Bits
Access
Mnemonic
Reset
Description
D31:06
Read only;
hard-wired to
0
Reserved
N/A
N/A
Table 261: PCI Arbiter Interrupt Status register
Bits
Access
Mnemonic
Reset
Description
Table 260: PCI Arbiter Configuration register
Reserved
CCLK
RUN
PCI
SERR
PCI
BRK_
M3
PCI
BRK_
M0
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
30
Reserved
PCI
BRK_
M2
PCI
BRK_
M1