Digi NS9750 User Manual
Page 258
R e g i s t e r s
2 3 4
N S 9 7 5 0 H a r d w a r e R e f e r e n c e
Static Memory Write Enable Delay 0–3 registers
Address: A070 0204 / 0224 / 0244 / 0264
The Static Memory Write Enable Delay 0–3 registers allow you to program the delay
from the chip select to the write enable assertion. The Static Memory Write Enable
Delay register is used in conjunction with the Static Memory Write Delay registers, to
control the width of the write enable signals. It is recommended that these registers
be modified during system initialization, or when there are no current or outstanding
transactions. Wait until the memory controller is idle, then enter low-power or
disabled mode.
Register bit assignment
Bits
Access
Mnemonic
Description
D31:04
N/A
Reserved
N/A (do not modify)
D03:00
R/W
WWEN
Wait write enable (WAITWEN)
0000
One HCLK cycle delay between assertion of chip select
and write enable (reset value on
reset_n
).
0001–1111
(n+1) HCLK cycle delay, where the delay is
(WAITWEN+1) x t
HCLK
Delay from chip select assertion to write enable.
Table 160: Static Memory Write Enable Delay 0–3 registers
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
30
Reserved
Reserved
WWEN