Pll configuration register – Digi NS9750 User Manual
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S y s t e m C o n t r o l M o d u l e
PLL Configuration register
Address: A090 0188
The PLL Configuration register configures the PLL.
Register bit assignment
D00
R/W
IRAM0
0x0
Internal register access mode bit 0
0
Allow access to internal registers using
PRIVILEGED mode only
1
Allow access to internal registers using
PRIVILEGED or USER mode.
Bits
Access
Mnemonic
Reset
Description
Table 187: Miscellaneous System Configuration and Status register
Bits
Access
Mnemonic
Reset
Description
D31:26
N/A
Reserved
N/A
N/A
D25
R
PLLBS
HW strap
gpio[19]
PLL bypass status
Status register to determine the powerup strapping
settings or the new settings as changed by software.
D24:23
R
PLLFS
HW strap
gpio[2],
gpio[0]
PLL FS status [1:0]
Status register to determine the powerup strapping
settings or the new settings as changed by software.
D22:21
R
PLLIS
HW strap
gpio[24],
gpio[22]
PLL IS status[1:0]
Status register to determine the powerup strapping
settings or the new settings as changed by software.
Table 188: PLL Configuration register
PLLBW
FSEL
CPCC
NDSW
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
PLLSW
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
30
PLLBS
PLLFS
PLLIS
PLLND
Reserved
Reserved