Digi NS9750 - Manual (Page 433)

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P C I - t o - A H B B r i d g e
window size of each Base Address register is hardwired (see Table 257 on page 417),
but each register can be enabled or disabled using the ENBAR0–ENBAR5 bits in the PCI
Miscellaneous Support register (see page 426) in the PCI arbiter.
The bridge supports PCI to AHB memory address translation using the PCI Bridge PCI
to AHB Memory Address Translate 0/1(see page 439) and PCI Bridge Address
Translation Control (see page 441) registers. The address translation scheme provides
a separate translation value for each of the six Base Address registers. The
translation window size is the same as the size of the corresponding register.
The
MALTxVAL
fields in the PCI Bridge PCI to AHB Memory Address Translate 0/1
registers (see page 439 and page 440) control the translation for each of the six Base
Address registers. For example, if
MALT1VAL
is set to
0x08
, an access to
0xFC00_0000
on
the PCI bus that hits Base Address register 1 is mapped to
0x2000_0000
on the AHB bus.
The
MALT_EN
bit in the PCI Bridge Address Translation Control register determines
whether PCI to AHB address translation is enabled:
When set to 1,
MALT_EN
enables address translation.
When set to 0, no address translation takes place, and the AHB and PCI
addresses are identical.
The external PCI bus is allowed access only to NS9750’s system memory. The
MALTxVAL
values, therefore, should be programmed only to map addresses in the
lower 2 GB of NS9750’s 4 GB address space (
0x0000_0000 -> 0x7FFF_FFFF
)
Interrupts
The bridge generates an interrupt to the AHB bus, for either AHB or PCI bus errors. An
AHB bus error interrupt is generated when the AHB master receives an ERROR
response to a transaction it initiated. The status bit for this interrupt,
AHBERR
, is in
the PCI Bridge Interrupt Status register (see page 434).
A PCI bus error interrupt is generated for any of these PCI conditions:
Address or data parity error detected (
DPE
, see "Detected parity error" on
page 415)
Bridge-generated system error (
SERR#
, see "Signaled system error" on page
415)
Bridge receives a master abort (
RMA
, see "Received master abort" on page
415)