Digi NS9750 - Manual (Page 876)

I n d e x - 6
DMA read. See also DMA memory-to-
peripheral transfers. 471
DMA Status and Interrupt Enable
register 494
DMA Status/Interrupt Enable register 516
DMA system
5
DMA transfer
executing 474
two-channel transfer
external-peripheral-initiated 474
processor-initated 474
DMA transfer status
506
-
508
DMA write. See also DMA peripheral-to-
memory transfers. 471
documentation
conventions xxi
domain faults
101
downstream port (USB)
708
downstream transactions 405
DSP 78
dummy default master 257
dynamc memory controller
address mapping
163
-
201
Dynamic Memory Active Bank A to Active
Bank B Time register 222
Dynamic Memory Active to Active
Command Period register
219
Dynamic Memory Active to Precharge
Command Period register 214
Dynamic Memory Auto refresh Period
register
220
Dynamic Memory Configuration 0-3
registers 225
address mapping 226
Dynamic Memory Control register 208
dynamic memory controller 162 - 201
write protection
162
dynamic memory controller, access
sequencing and memory width 162
Dynamic Memory Data-in to Active
Command Time register
217
Dynamic Memory Exit Self-refresh
register 221
Dynamic Memory Last Data Out to Active
Time register
216
Dynamic Memory Load Mode register to
Active Command Time
register
223
Dynamic Memory Precharge Command
Period register 213
Dynamic Memory RAS and CAS Delay 0-3
registers 229
Dynamic Memory Read Configuration
register 212
Dynamic Memory Refresh Timer
register 210
Dynamic Memory Self-refresh Exit Time
register
215
Dynamic Memory Write Recovery Time
register 218
E
ECP mode
673
-
674
forward transfer cycles
673
host processing sequence
example 674
reverse transfer cycles 674
electrical characteristics
788
-
789
electrical specifications. See Timing .
ENABLE bit, Ethernet 326
enable/disable interrupts for BBus
DMA 537
Endian configuration
411
Endian Configuration register
539
Endpoint Descriptor 0-11 registers 766
Ethernet communication module 315 - 401
Back-to-Back Inter-Packet-Gap