Fifo interrupt enable registers – Digi NS9750 User Manual
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U S B D e v i c e E n d p o i n t F I F O C o n t r o l a n d D a t a r e g i s t e r s
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N S 9 7 5 0 H a r d w a r e R e f e r e n c e
FIFO Interrupt Enable registers
The FIFO Interrupt Enable registers contain the interrupt enable information for the
device block FIFOs. All interrupts are enabled by writing a 1 and are disabled by
writing a 0. The endpoint to register field mapping is identical to the FIFO Interrupt
Status registers.
FIFO Interrupt Enable 0 register
Address: 9010 3004
Register bit assignment
Bits
Access
Mnemonic
Reset
Description
D31:16
N/A
Not used
0x0000
Always read as 0x0000.
D15
R/W
ACK2
0
Generate an interrupt when ACK2 in FIFO Interrupt
Status 0 register is asserted.
D14
R/W
NACK2
0
Generate an interrupt when NACK2 in FIFO Interrupt
Status 0 register is asserted.
D13
R/W
ERROR2
0
Generate an interrupt when ERROR2 in FIFO Interrupt
Status 0 register is asserted.
D12:08
N/A
Reserved
N/A
Not valid in DMA mode.
D07
R/W
ACK1
0
Generate an interrupt when ACK1 in FIFO Interrupt
Status 0 register is asserted.
D06
R/W
NACK1
0
Generate an interrupt when NACK1 in FIFO Interrupt
Status 0 register is asserted.
D05
R/W
ERROR1
0
Generate an interrupt when ERROR1 in FIFO Interrupt
Status 0 register is asserted.
D04:00
N/A
Reserved
N/A
Not valid in DMA mode.
Table 454: FIFO Interrupt Enable 0 register
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
30
Reserved
ERROR
2
Reserved
ACK2 NACK
2
Reserved
ACK1 NACK
1
ERROR
1