Digi NS9750 - Manual (Page 829)

w w w . d i g i e m b e d d e d . c o m 8 0 5
T i m i n g
Static RAM read cycles with 0 wait states
Figure 113: Static RAM read cycles with 0 wait states timing
WTRD = 1
WOEN = 1
If the PB field is set to 1, all four
byte_lane
signals will go low for 32-bit,
16-bit, and 8-bit read cycles.
If the PB field is set to 0, the
byte_lane
signal will always be high.
M24 M23
M28 M27
M20 M19
M18 M17
M26
M25
CPU clock / 2
data<31:0>
addr<27:0>
st_cs_n<3:0>
oe_n
byte_lane<3:0>