Digi NS9750 - Manual (Page 144)

F e a t u r e s
1 2 0 N S 9 7 5 0 H a r d w a r e R e f e r e n c e
8
More boot, initialization, or application code is executed.
Example: Boot from flash, SDRAM remapped after boot
The system is set up as:
Chip select 1 is connected to the boot flash device.
Chip select 4 is connected to the SDRAM to be remapped to
0x00000000
after
boot.
The boot sequence is as follows:
1
At power-on, the reset chip select 1 is mirrored into chip select 4 (and chip
select 0). The following signals are configured so the nonvolatile memory device
can be accessed:
– boot_strap[4:3]
– gpio[49]
2
When the power-on reset (
reset_n
) and AHB reset (
HRESETn
) go inactive, the
processor starts booting from
0x00000000
in memory.
3
The software programs the optimum delay values in flash memory so the boot
code can run at full speed.
4
The code branches to chip select 1 so the code can continue executing from the
non-remapped memory location.
5
The appropriate values are programmed into the memory controller to configure
chip select 4, and the memory device is initialized.
6
The address mirroring is disabled by clearing the address mirror (M) field in the
Control register (see page 205).
7
The ARM reset and interrupt vectors are copied from flash memory to SDRAM
that can then be accessed at address
0x00000000
.
8
More boot, initialization, or application code is executed.