Digi NS9750 - Manual (Page 879)

I - I n d e x - 9
fly-by mode 502
fly-by peripheral to memory
operations 505
Forward Address register 703
Forward Command DMA Control
register
689
Forward Command FIFO Read register
686
Forward Data DMA Control register 690
Forward Data FIFO Read register 687
FULL bit 476 , 506
FULL bit, Ethernet 326 , 328
G
gated timer
263
GEN ID register 311
general purpose I/O. See also GPIO .
general purpose timers and counters 6
general purpose timers/counters 263
General Statistics registers (Ethernet)
377
Carry Register 1
378
Carry Register 1 Mask register 380
Carry Register 2 379
Carry Register 2 Mask register 382
generating interrupts, LCD 575
Global Control and Status register
717
Global Interrupt Enable register 720
Global Interrupt Status register 721
GPIO Configuration register options 528
GPIO Configuration registers 524 - 529
GPIO Control registers
529
-
532
GPIO MUX pinout
34
GPIO Status registers 532 - 535
GPTC. See general purpose timers/
counters.
Granularity Count register
702
grayscaler
574
H
handling USB-IN packet errors 715
handling USB-OUT packet errors 715
Harvard-cached architecture 48
HcBulkCurrentED register
744
HcBulkHeadED register 743
HcCommandStatus register 730
HcControl register 727
HcControlCurrentED register 742
HcControlHeadED register 741
HcDoneHead register
746
HcFmInterval register 747
HcFmNumber register 749
HcFmRemaining register 748
HcHCCA register 739
HcInterruptDisable register
737
HcInterruptEnable register
735
HcInterruptStatus register 733
HcLsThreshold register 751
HcPeriodCurrentED register 740
HcPeriodicStart register 750
HCRevision register
726
HcRhDescriptorA register 753
HcRhDescriptorB register 755
HcRhPortStatus1 register 759
HcRhStatus register 756
high-speed bus architecture 255
high-speed peripheral subsystem
255
horizontal axis panel 580
horizontal timing restrictions,
LCDTiming0 581
host block, USB 708 , 710 , 712 - 714
control and status
712
packet data flow 713
host controller communication area 739
hsel_x signal 261