Pci configuration 2 register, Pci clocks of, Being negated. this is the time allowed from – Digi NS9750 User Manual
Page 454: Register bit assignment, Table 265: pci configuration 1 register
P C I b u s a r b i t e r
4 3 0
N S 9 7 5 0 H a r d w a r e R e f e r e n c e
Register bit assignment
PCI Configuration 2 register
Address: A030 0018
The PCI Configuration 2 register contains the values that will be read from the PCI
Subsystem ID and PCI Subsystem Vendor ID registers.
Change these fields only during system initialization, when there is no PCI activity. In
a system where NS9750 is not the host, these fields must be programmed within 2
25
PCI clocks of
RST#
being negated. This is the time allowed from
RST#
negated to the
first configuration cycle on the PCI bus.
Bits
Access
Mnemonic
Reset
Description
D31:08
R/W
CLASS_CODE
0x060000
Class code value
Value to be inserted into PCI Class Code register.
Defaults to class code for a
host/PCI bridge (0x060000).
D07:00
R/W
REVISION_ID
0x00
Revision ID value
Value to be inserted into the PCI Revision ID
register. Defaults to
0x00
.
Table 265: PCI Configuration 1 register
CLASS_CODE
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
30
CLASS_CODE
REVISION_ID
SUBSYSTEM_ID
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
30
SUBVENDOR_ID