Digi NS9750 User Manual
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M e m o r y C o n t r o l l e r
Dynamic Memory RAS and CAS Delay 0–3 registers
Address: A070 0104 / 0124 / 0144 / 0164
The Dynamic Memory RAS and CAS Delay 0–3 registers allow you to program the RAS
and CAS latencies for the relevant dynamic memory. It is recommended that these
registers be modified during system initialization, or when there are no current or
outstanding transactions. Wait until the memory controller is idle, then enter low-
power or disabled mode.
Note:
The values programmed into these registers must be consistent with the
values used to initialize the SDRAM memory device.
Register bit assignment
Bits
Access
Mnemonic
Description
D31:10
N/A
Reserved
N/A (do not modify)
D09:08
R/W
CAS
CAS latency
00
Reserved
01
One clock cycle, where the RAS to CAS latency (RAS) and
CAS latency (CAS) are defined in CLK cycles
10
Two clock cycles
11
Three clock cycles (reset value on
reset_n)
D07:02
N/A
Reserved
N/A (do not modify)
D01:00
R/W
RAS
RAS latency (active to read.write delay)
00
Reserved
01
One clock cycle, where the RAS to CAS latency (RAS) and
CAS latency (CAS) are defined in CLK cycles
10
Two clock cycles
11
Three clock cycles (reset value on
reset_n
)
Table 158: Dynamic Memory RAS and CAS Delay 0–3 registers
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
30
Reserved
Reserved
CAS
Reserved
RAS