Digi NS9750 User Manual
Page 792
U S B D e v i c e E n d p o i n t F I F O C o n t r o l a n d D a t a r e g i s t e r s
7 6 8
N S 9 7 5 0 H a r d w a r e R e f e r e n c e
Table 448 describes the fixed relationship from endpoint to interface FIFO to DMA
channel for all registers described in the remainder of the chapter.
9010 30A4
FIFO Packet Control #10
9010 30A8
FIFO Packet Control #11
9010 30AC
FIFO Packet Control #12
9010 30B0
FIFO Packet Control #13
9010 3100
FIFO Status and Control #1
9010 3108
FIFO Status and Control #2
9010 3110
FIFO Status and Control #3
9010 3118
FIFO Status and Control #4
9010 3120
FIFO Status and Control #5
9010 3128
FIFO Status and Control #6
9010 3130
FIFO Status and Control #7
9010 3138
FIFO Status and Control #8
9010 3140
FIFO Status and Control #9
9010 3148
FIFO Status and Control #10
9010 3150
FIFO Status and Control #11
9010 3158
FIFO Status and Control #12
9010 3160
FIFO Status and Control #13
DMA channel
FIFO
EP number
1
1
0 (CTRL-Out)
2
2
0 (CTRL-In)
3
3
1
4
4
2
5
5
3
Table 448: FIFO to DMA channel to endpoint map
Address
Register
Table 447: USB Device Endpoint FIFO Control registers address map