Ethernet timing – Digi NS9750 User Manual
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T i m i n g
Ethernet timing
Note:
All AC characteristics are measured with 10pF, unless otherwise noted.
Table 470 describes the values shown in the Ethernet timing diagrams (Figure 119 and
Figure 120).
Notes:
1
Minimum specification is for fastest AHB bus clock of 100 MHz. Maximum specification is for
slowest AHB bus clock of 50 MHz.
2
C
load
= 10pf for all outputs and bidirects.
3
No setup and hold requirements for
cam_reject
because it is an asynchronous input. This is also true for RMII
PHY applications.
Parameter
Description
Min
Max
Unit
Notes
E1
MII tx_clk to txd, tx_en, tx_er
3
11
ns
2
E2
MII rxd, rx_en, rx_er setup to rx_clk rising
3
ns
E3
MII rxd, rx_en, rx_er hold from rx_clk rising
1
ns
E4
mdio (input) setup to mdc rising
10
ns
E5
mdio (input) hold from mdc rising
0
ns
E6
mdc to mdio (output)
18
38
ns
1,2
E7
mdc period
80
ns
E8
RMII ref_clk to txd, tx_en
3
12
ns
2
E9
RMII rxd, crs, rx_er setup to ref_clk rising
3
ns
E10
RMII rxd, crs, rx_er hold from ref_clk rising
1
ns
E11
MII rx_clk to cam_req
3
10
ns
E12
MII cam_reject setup to rx_clk rising
N/A
ns
3
E13
MII cam_reject hold from rx_clk rising
N/A
ns
3
Table 470: Ethernet timing characteristics