Quantum Data 881 User Manual
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Chapter 14 DisplayPort Link Layer Testing
Running the Link Layer compliance test for DisplayPort
source devices
The 882E supports the running of an Link Layer compliance test on DisplayPort sources.
The Link Layer compliance test system enables developers of DisplayPort products to
perform a fast and comprehensive Link Layer compliance test. Because the 882E can
emulate DisplayPort Link Layer sink devices it can perform a complete Link Layer
compliance test on any source.
The Link Layer compliance test can be run entirely through the 882E front panel or
through the command line. The DisplayPort commands enable you to run a specific
subset of the tests in the series of tests.
Note: While running the Link Layer compliance test on sink devices, you can monitor the
transactions using the optional Auxiliary Channel Analyzer (ACA) application. For
procedures on this “
Monitoring the DisplayPort auxiliary channel
The following table describes the tests that can be performed.
Index
Test
Description
0
4.2.1.1
Source DUT Retry on No-Reply During Aux Read after Hot
Plug Event
1
4.2.1.2
Source Retry on Invalid Reply During Aux Read after Hot
Plug Event
2
4.2.2.1
EDID Read upon Hot Plug Event
3
4.2.2.2
DPCD Receiver Capability Read upon Hot Plug Event
4
4.2.2.3
EDID Read
5
4.2.2.4
EDID Absence Detection
6
4.2.2.5
EDID Corruption Detection
7
4.3.1.1
Successful Link Training Upon Hot Plug detect
8
4.3.1.2
Successful Link Training at All Supported Lane Counts and
Link Speeds
9
4.3.1.3
Successful Link Training with Request of Higher Differential
Voltage Swing during Clock Recovery Sequence
10
4.3.1.4
Successful Link Training to a Lower Link Rate #1: Iterate at
Maximum Voltage Swing
11
4.3.1.5
Successful Link Training to a Lower Link Rate #2: - Iterate
at Minimum Voltage Swing
12
4.3.1.6
Successful Link Training with Request of a Higher
Pre-emphasis Setting During Channel Equalization
Sequence