Freescale Semiconductor StarCore SC140 User Manual
Sc140 dsp core
Table of contents
Document Outline
- SC140 DSP Core Reference Manual
- Chapter1 Introduction
- Chapter2 Core Architecture
- 2.1 Architecture Overview
- 2.2 DALU
- 2.3 Address Generation Unit
- 2.4 Memory Interface
- Chapter3 Control Registers
- Chapter4 Emulation and Debug (EOnCE)
- 4.1 Debugging System
- 4.2 Overview of the Combined JTAG and EOnCE Interface
- 4.3 Main Capabilities of the EOnCE Module
- 4.4 EOnCE Enabling and Power Considerations
- 4.5 EOnCE Module Internal Architecture
- 4.6 EOnCE Register Addressing
- 4.7 EOnCE Controller Registers
- 4.7.1 EOnCE Command Register (ECR)
- 4.7.2 EOnCE Status Register (ESR)
- 4.7.3 EOnCE Monitor and Control Register (EMCR)
- 4.7.4 EOnCE Receive Register (ERCV)
- 4.7.5 EOnCE Transmit Register (ETRSMT)
- 4.7.6 EE Signals
- 4.7.7 Core Command Register (CORE_CMD)
- 4.7.8 PC of the Exception ExecutionSet (PC_EXCP)
- 4.7.9 PC of the Next ExecutionSet (PC_NEXT)
- 4.7.10 PC of Last ExecutionSet (PC_LAST)
- 4.7.11 PC Breakpoint Detection Register (PC_DETECT)
- 4.8 Event Counter Registers
- 4.9 Event Detection Unit (EDU) Channels and Registers
- 4.10 Event Selector (ES) Registers
- 4.11 Trace Unit Registers
- Chapter5 Program Control
- 5.1 Pipeline
- 5.2 Instruction Grouping
- 5.3 Instruction Timing
- 5.4 Hardware Loops
- 5.5 Stack Support
- 5.6 Working Modes
- 5.7 Processing States
- 5.8 Exception Processing
- Chapter6 Instruction Set Accelerator Plug-In
- Chapter7 Programming Rules
- 7.1 VLES Sequencing Semantics
- 7.2 VLES Grouping Semantics
- 7.3 SC140 Pipeline Exposure
- 7.4 Programming Rule Notation
- 7.5 Static Programming Rules
- 7.6 Dynamic Programming Rules
- 7.7 Programming Guidelines
- 7.8 LPMARK Rules
- 7.9 NOP Definition
- AppendixA SC140 DSP Core Instruction Set
- A.1 Introduction
- A.2 Instructions
- A.2.1 Instruction Definition Layout
- ABS
- ADC
- ADD
- ADD2
- ADDA
- ADDL1A
- ADDL2A
- ADDNC.W
- ADR
- AND
- AND
- AND.W
- ASL
- ASL2A
- ASLA
- ASLL
- ASLW
- ASR
- ASRA
- ASRR
- ASRW
- BF
- BFD
- BMCHG
- BMCHG.W
- BMCLR
- BMCLR.W
- BMSET
- BMSET.W
- BMTSET
- BMTSET.W
- BMTSTC
- BMTSTC.W
- BMTSTS
- BMTSTS.W
- BRA
- BRAD
- BREAK
- BSR
- BSRD
- BT
- BTD
- CLB
- CLR
- CMPEQ
- CMPEQ.W
- CMPEQA
- CMPGT
- CMPGT.W
- CMPGTA
- CMPHI
- CMPHIA
- CONT
- CONTD
- DEBUG
- DEBUGEV
- DECA
- DECEQ
- DECEQA
- DECGE
- DECGEA
- DI
- DIV
- DMACSS
- DMACSU
- DOENn
- DOENSHn
- DOSETUPn
- EI
- EOR
- EOR
- EOR.W
- EXTRACT
- EXTRACTU
- IADDNC.W
- IFc
- ILLEGAL
- IMAC
- IMACLHUU
- IMACUS
- IMPY
- IMPY.W
- IMPYHLUU
- IMPYSU
- IMPYUU
- INC
- INC.F
- INCA
- INSERT
- JF
- JFD
- JMP
- JMPD
- JSR
- JSRD
- JT
- JTD
- LPMARKx
- LSLL
- LSR
- LSRA
- LSRR
- LSRW
- MAC
- MACR
- MACSU
- MACUS
- MACUU
- MARK
- MAX
- MAX2
- MAX2VIT
- MAXM
- MIN
- MOVE.2F
- MOVE.2L
- MOVE.2W
- MOVE.4F
- MOVE.4W
- MOVE.B
- MOVE.F
- MOVE.L
- MOVE.L
- MOVE.L
- MOVE.W
- MOVE.W
- MOVEc
- MOVES.2F
- MOVES.4F
- MOVES.F
- MOVEU.B
- MOVEU.L
- MOVEU.W
- MOVEU.W
- MPY
- MPYR
- MPYSU
- MPYUS
- MPYUU
- NEG
- NOP
- NOT
- NOT
- NOT.W
- OR
- OR
- OR.W
- POP
- POPN
- PUSH
- PUSHN
- RND
- ROL
- ROR
- RTE
- RTED
- RTS
- RTSD
- RTSTK
- RTSTKD
- SAT.F
- SAT.L
- SBC
- SBR
- SKIPLS
- STOP
- SUB
- SUB2
- SUBA
- SUBL
- SUBNC.W
- SXT.x
- SXTA.x
- TFR
- TFRA
- TFRA
- TFRc
- TSTEQ
- TSTEQA.x
- TSTGE
- TSTGEA.L
- TSTGT
- TSTGTA
- VSL
- WAIT
- ZXT.x
- ZXTA.x
- A.2.1 Instruction Definition Layout
- AppendixB StarCore Registry
- Index