Event counter register (ecnt_ctrl) -51, Ecnt_ctrl description -51, Table 4-18 describes the ecnt_ctrl fields – Freescale Semiconductor StarCore SC140 User Manual
Page 161
Event Counter Registers
SC140 DSP Core Reference Manual
4-51
ascertain the number of cycles needed by a device to get from a starting address to an ending address, in
the following manner:
1. Write $7FFF FFFF to the ECNT_VAL register.
2. Configure ECNT to count the internal clock.
3. Program ECNT to be enabled upon EDCAi detection.
4. Program EDCAi to detect the starting address.
5. Program EDCAj to detect the ending address.
6. Program ES to generate a debug exception upon EDCAj detection.
The following stages are:
1. Detection of the start address which enables the counter and to start counting.
2. Detection of the final address which generates a debug exception.
3. ISR of the debug exception which disables the counter, reads the counter contents
(ECNT_VAL register), and subtracts the cycles of the interrupt service routine overhead.
This value gives the cycle count between the count enabling and the ending address.
When the trace buffer operates in counter mode, each destination address that is put into the trace buffer is
followed by the value of the counter register. The trace buffer can also be configured to write both the
values of the counter and extension counter with each trace package. For more information, see
Section 4.11.1, “Trace Buffer Control Register (TB_CTRL).”
The counter can be configured to count the number of traced entries. In case the tracing includes the
counter values themselves, they are counted as well.
Figure 4-20 displays the configuration of ECNT_CTRL. The shaded bits are reserved and should be
initialized with zeros for future software compatibility.
Figure 4-20. Event Counter Register (ECNT_CTRL)
Table 4-18 describes the ECNT_CTRL fields.
BIT 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
BIT 0
TEST
EXT
ECNTEN
ECNTWHAT
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4-18. ECNT_CTRL Description
Name
Description
Settings
R
Bits 15–10
Reserved
TEST
Bit 9
Reserved for Test
0 = Normal operation
1 = Reserved for test
EXT
Bit 8
Extended Mode of Operation Bit —
See
Section 4.5.2, “Event Counter,”
0 = ECNT operates in regular mode
1 = ECNT operates in extended mode