Deca, Decrement a register (agu), Example – Freescale Semiconductor StarCore SC140 User Manual
Page 453: Instruction formats and opcodes instruction fields, Operation assembler syntax, Deca r0, Where #u5 = 1
DECA
SC140 DSP Core Reference Manual
A-139
DECA
Decrement a Register (AGU)
DECA
Description
Status and Conditions that Affect Instruction
Status and Conditions Changed by Instruction
None.
Example
deca r0
Instruction Formats and Opcodes
Instruction Fields
Rx
RRRR
AGU Source/Destination Register
Operation
Assembler Syntax
Rx – 1
→ Rx
DECA Rx
DECA Rx
Subtracts one from an AGU register (Rx). SP cannot be used as a destination of this instruction.
Note:
The assembler maps this instruction to SUBA #u5,Rx;
where #u5 = 1.
Register Address
Bit Name
Description
MCTL[31:0]
AM3–AM0
Address modification bits when updating R0–R7. Otherwise, the
instruction is not affected by MCTL.
Register/Memory Address
Before
After
MCTL
$0000 0000
R0
$074F 312A
$074F 3129
Instruction
Words Cycles Type
Opcode
15
8
7
0
DECA Rx
1
1
2
1
1
1
0
R R R R
0
1
1
i
i
i
i
i
0000
N0
0100
—
1000
R0
1100
R4
0001
N1
0101
—
1001
R1
1101
R5
0010
N2
0110
—
1010
R2
1110
R6
0011
N3
0111
SP
1011
R3
1111
R7
Note:
This instruction can specify R8-R15 as operands by using a high register prefix.