Freescale Semiconductor StarCore SC140 - Manual (Page 156)

4-46 SC140 DSP Core Reference Manual
EOnCE Controller Registers
The functionality of EE signals when programmed as an input depends on the programming of the EDU
and the ES. See
Section 4.9, “Event Detection Unit (EDU) Channels and Registers,” for further details.
Table 4-16 describes the EE_CTRL fields.
Table 4-16. EE_CTRL Description
Name Description Settings
EEDDEF
Bit 15 EED Definition — Programs the EED signal.
As an output of the EED, the EEDDEF bit can
indicate detection by the EDCD, working as a
toggle. As an input to the EOnCE, EED can be
programmed to enable the EDCD. EED
cannot disable EDCD. 0 = Output, detection by EDCD
1 = Input, enables EDCD
R
Bits
14–11 Reserved
EE5DEF
Bit 10 EE5 Definition — Programs the EE5 signal.
Programmed as an output of the EOnCE, EE5
can indicate detection by EDCA5, working as
a toggle. Programmed as an input to the
EOnCE, EE5 can be programmed to enable
EDCA5. EE5 cannot disable EDCA5. 0 = Output, detection by EDCA5
1 = Input, enables EDCA5
EE4DEF
Bits 9–8 EE4 Definition — Programs the EE4 signal.
Programmed as an output of the EOnCE, EE4
can indicate detection by EDCA4, working as
a toggle. It can also indicate that the ETRSMT
register was written by the core. Programmed
as an input to the EOnCE according to the
programming of the EDU and the ES, EE4 can
be programmed to enable EDCA4 or to
generate one of the EOnCE events. EE4
cannot disable EDCA4. 00 = Output, detection by EDCA4
01 = Output, data in ETRSMT register ready
10 = Reserved
11 = Input, enables EDCA4 or generates an EOnCE
event
EE3DEF
Bits 7–6 EE3 Definition — Programs the EE3 signal.
Programmed as an output of the EOnCE, EE3
can indicate detection by EDCA3, working as
a toggle. It can also indicate that the ERCV
register is full. Programmed as an input to the
EOnCE according to the programming of the
EDU and the ES, EE3 can be programmed to
enable EDCA3 or to generate one of the
EOnCE events. EE3 cannot disable EDCA3. 00 = Output, detection by EDCA3
01 = ERCV register full
10 = Reserved
11 = Input, enables EDCA3 or generates an EOnCE
event