Freescale Semiconductor StarCore SC140 - Manual (Page 576)

A-262 SC140 DSP Core Reference Manual
MOVE.4W
MOVE.4W
Move Four Integer Words
MOVE.4W
to/from a Register Quad (AGU)
Description
Status and Conditions that Affect Instruction
Status and Conditions Changed by Instruction
Example
Operation Assembler Syntax
(EA)
↔ Da:Db:Dc:Dd
MOVE.4W (EA),Da:Db:Dc:Dd {0
≤ EA < 2
32 ,Q}
MOVE.4W Da:Db:Dc:Dd,(EA){0
≤ EA < 2
32 ,Q}
MOVE.4W (EA),Da:Db:Dc:Dd
MOVE.4W Da:Db:Dc:Dd,(EA)
Moves four signed integer words from memory to a data register quad (Da:Db:Dc:Dd), or from the register
quad to memory. The effective memory address of the four words is obtained from an address register with
an optional offset or post-increment (EA). Each word is stored in the LP of its respective data register.
The first operand (Da) will be moved to or from the lower memory address (EA). The second operand (Db)
will be moved to or from memory address (EA + 2). The third operand (Dc) will be moved to or from
memory address (EA + 4). And, the fourth operand (Dd) will be moved to or from memory address (EA +
6). In order to keep this behavior in both big endian and little endian modes, the core will drive or interpret
the data bus differently in each mode. See
Section 2.4.1, “SC140 Endian Support,” on page 2-56, for more
detail on bus and memory behavior for each mode.
The address register values used with this instruction must be a multiple of 8, quad word-aligned.
Register Address Bit Name Description
MCTL[31:0] AM3–AM0 Address modification bits when updating R0–R7. Otherwise, the
instruction is not affected by MCTL.
EMR[16] BEM Set if big endian mode, cleared if little endian mode.
Register Address Bit Name Description
Ln L Clears the Ln bit in the destination registers.
SIGN EXTENSION
SIGN EXTENSION
SIGN EXTENSION
39 0 16
SIGN EXTENSION
Da
Db
Dc
Dd
(EA)
(EA + 2)
(EA + 4)
(EA + 6)