Freescale Semiconductor StarCore SC140 - Manual (Page 645)

NEG
SC140 DSP Core Reference Manual A-331
N-R
NEG
Negate (DALU)
NEG
Description
Status and Conditions that Affect Instruction
Status and Conditions Changed by Instruction
Example
neg d3
0000 0111 0110 0101 0001 0010 0011 0101
invert 1111 1000 1001 1010 1110 1101 1100 1010
add one 1111 1000 1001 1010 1110 1101 1100 1011
Operation Assembler Syntax
0 – Dn
→ Dn
NEG Dn
NEG Dn
Negates the contents of a source data register (Dn) and stores the 40-bit two’s complement result in a
destination data register (Dn).
Register Address Bit Name Description
SR[2] SM If set, selects 32-bit arithmetic saturation mode.
SR[5:4] S[1:0] Scaling mode bits determine which bits in the result are used in the
Ln bit calculation.
Register Address Bit Name Description
Ln L If not in arithmetic saturation mode (SR [SM] = 0), calculates and
updates the Ln bit in the destination register. If in arithmetic
saturation mode (SR [SM] = 1), clears the Ln bit in the destination
register.
EMR[2] DOVF Set if the result cannot be represented in 40 bits, or if the result
saturates to 32 bits in saturation mode.
Register/Memory Address Before After
SR $00E0 0000
L3:D3 $0:$00 0765 1235 $0:$FF F89A EDCB
EMR $0000 0000