Freescale Semiconductor StarCore SC140 - Manual (Page 291)

Dynamic Programming Rules
SC140 DSP Core Reference Manual 7-41
Rule L.G.5
A loop having one or two VLES must be enabled by a DOENSHn instruction. A loop having three or more
VLES must be enabled by a DOENn instruction.
Example 7-76. Enabling Short and Long Loops
doen1 #5 ; not allowed
dosetup1 label1
skipls label2
loopstart1
label1
move.l d1,(r1)+
addnc.w #1,d1,d1
loopend1
label2 nop
7.6 Dynamic Programming Rules
Dynamic programming rules cannot be detected by the assembler examining the source code, because they
depend on the run-time execution trace. These rules can be detected by the simulator examining the SC140
visible and hidden registers and simulation trace. The simulator detects all dynamic rules that occur during
its execution. The simulator cannot detect programming rules in binary encodings that were not executed.
Dynamic rule detection depends on the test coverage of the programmer’s test suite. Programmers should
exercise all COF destinations, exception service routines, and system configurations (such as conditional
assembly directives) in the simulation trace so the simulator detects all dynamic programming rules. The
simulation trace should also exercise all data dependencies of conditional COF instructions (such as Bc
and Jc), conditional instructions (MOVEc and TFRc) and conditional groups or subgroups (IFc).
7.6.1 AGU Dynamic Rules
Rule A.2a
At least one cycle is required between when a MOVE-like instruction writes Bn or Mn register as a data
operand and a MOVE or an AGU arithmetic instruction using the same register for a modulo calculation
(even in the case that Bn is referred to as R
n+8) . This rule applies only if these registers are actually used in
a modulo calculation as determined by the actual value in MCTL.
Example 7-77. Bn, Mn Write to AGU Use
move.l #$000000f, MCTL ; r0 only has modulo addressing
move.l d0,b0
move.w (r0)+,d1
; Not allowed
pop d0,m1
adda r9,r1
; Allowed