Freescale Semiconductor StarCore SC140 - Manual (Page 315)

SC140 DSP Core Reference Manual A-1
Appendix A
SC140 DSP Core Instruction Set
A.1 Introduction
This appendix describes in detail the SC140 instruction set, its encoding, and its syntax. The first pages of
this appendix contain information common to all of the instructions such as the conventions, notation, and
syntax used in the Appendix. Next, the encoding for the prefix words is given. Then, the names and simple
descriptions of the instructions are listed in functional groups. At the end of the introductory section, a
single page describes the format of the instruction descriptions, which are listed in alphabetical order
through the bulk of the Appendix.
Each non-prefix instruction activates one functional unit in the SC140 architecture. The architecture can be
viewed as several functional units operating in parallel:
• Four arithmetic logic units (ALUs)
• Two address arithmetic units (AAUs)
• One bit mask unit (BMU)
• One program controller (PSEQ)
Several instructions can be grouped together for parallel execution.
The instruction set has been designed to enable efficient parallel execution of DSP algorithms and control
code, using high-level language compilers, achieving maximum speed and minimum power consumption.
This extensive range of instruction capabilities also provides a very powerful assembly language for DSP
algorithms and general-purpose computing. Certain programming rules apply regarding the ability to
group instructions that activate the various units, because of their use of shared resources.