Freescale Semiconductor StarCore SC140 - Manual (Page 252)

7-2 SC140 DSP Core Reference Manual
VLES Grouping Semantics
• All instructions in a VLES execute in parallel. This means:
— The assembly source order of instructions and labels within an unconditional VLES does not
change the results, with one exception being the assembly source order determines which
instruction (if any) updates the carry bit. Because source order within an unconditional VLES is
not required for correct code execution, the assembler sometimes reorders instructions in the
VLES during the encoding process.
— All instruction source registers and memory locations are read in parallel when the VLES starts
execution. That is, the order that multiple reads occur does not change the results.
— After all sources are read, all grouped instructions operate on them in parallel.
— All instruction results are written to registers and memory locations in parallel when the VLES
finishes execution. Parallel memory writes must write to different locations so the order that
multiple writes occur does not change the results.
• Instructions in a VLES can execute conditionally. This means:
— A VLES without conditional instructions executes all instructions unconditionally.
— A VLES can have conditional instructions (such as Bc, Jc, MOVEc, TFRc, where c is the
execution condition). The conditional instruction executes if its condition is true. If its condition
is false, the instruction does not execute (becomes a NOP).
— The IFc instruction conditionally executes all instructions that follow it (in assembly source
order) until the next IFc instruction or the end of the VLES. Multiple IFc instructions in a VLES
form subgroups of instructions that are conditionally executed based on their associated IFc
condition. Multiple IFc subgroups having the same condition are in the same subgroup.
— Each unconditional instruction in an IFc group or subgroup executes if its IFc condition is true.
If its IFc condition is false, the instruction does not execute (becomes a NOP).
— Each conditional instruction in an IFc group or subgroup executes if the instruction’s condition
and its IFc condition are both true. If either condition is false, the instruction does not execute
(becomes a NOP).
• Only one carry-affecting instruction in a VLES may update the carry bit. This means:
— A VLES can have multiple carry-affecting instructions that execute in parallel.
— The carry-affecting instructions can execute unconditionally, or conditionally in an IFc group or
subgroup.
— The last (in assembly source order) carry-affecting instruction whose execution condition is true
updates the carry bit, while the other instructions in the VLES do not affect the carry bit.
— If no carry-affecting instructions execute, the carry bit is not affected.
• Even though the SC140 may execute instructions grouped in a VLES during different pipeline
stages, the assembly source grouping for parallel instruction execution is enforced.