Dmacsu, Multiply signed by unsigned and, Instruction formats and opcodes – Freescale Semiconductor StarCore SC140 User Manual
Page 469: Operation assembler syntax
DMACSU
SC140 DSP Core Reference Manual
A-155
DMACSU
Multiply Signed By Unsigned and
DMACSU
Accumulate With Right Shifted Data Register (DALU)
Description
Status and Conditions that Affect Instruction
None.
Status and Conditions Changed by Instruction
Example
dmacsu d2,d3,d5
Instruction Formats and Opcodes
Note:
** indicates serial grouping encoding.
Operation
Assembler Syntax
[Dn>>16] + Dc.H * Dd.L
→ Dn
(Dc signed, Dd unsigned)
DMACSU Dc,Dd,Dn
DMACSU Dc,Dd,Dn
Shifts Dn 16 bits to the right with bit 39 sign-extended into bits [39:24]. Adds the result to the product of a
signed fraction in Dc.H and an unsigned fraction in Dd.L. Places the result into Dn.
Dc and Dd are a data register pair. The operands are in the HP and LP of each register, respectively.
This instruction is optimized for multi-precision multiplication support.
Register Address
Bit Name
Description
Ln
L
Clears the Ln bit in the destination register.
Register/Memory Address
Before
After
D2
$FF F002 0000
D3
$00 0000 00D1
L5:D5
$0:$00 0001 0000
$0:$FF FFE5 E345
EMR
$0000 0000
Instruction
Words Cycles Type
Opcode
15
8
7
0
DMACSU Dc,Dd,Dn
1
1
1
0
*
1
0
1
1
F
F
F
1
1
1
0
0
e
e