Freescale Semiconductor StarCore SC140 - Manual (Page 273)

Static Programming Rules
SC140 DSP Core Reference Manual 7-23
Rule T.2.a
At least one VLES is required between an ISAP instruction that affects the T status bit in SR and a
conditional COF instruction.
Example 7-40. T Bit Update by ISAP and COF
{tsteq k0} ; tsteq is an ISAP instruction that
updates the T bit
jt r0 ; not allowed
{tsteq k0}
nop
jf _destination
; allowed
Rule T.2.b
At least two VLES are required between an ISAP instruction that affects the T status bit in SR and a
MOVET/MOVEF instruction.
Example 7-41. T Bit Update by ISAP and MOVET/MOVEF
{tsteq k0} ; tsteq is an ISAP instruction that
updates the T bit
movet r0,r1 ; not allowed
{tsteq k0}
nop
nop
movet r1,r2
; allowed
Rule T.2.c
At least two VLES are required between an ISAP instruction that affects the T status bit in SR and an AGU
instruction in an IFT/IFF group or subgroup. This rule does not apply to AGU instructions in an IFA
subgroup.
Example 7-42. T Bit Update by ISAP and IFT/IFF
{tsteq k0} ; tsteq is an ISAP instruction that
updates the T bit
ift move.l d0,d1 ; not allowed
{tsteq k0}
nop
nop
ift move.l d1,d2
; allowed
Rule SR.2
At least two VLES are required between a MOVE-like instruction that writes the SR register and an
instruction affected by a status bit in SR.