Freescale Semiconductor StarCore SC140 - Manual (Page 457)

DECEQA
SC140 DSP Core Reference Manual A-143
DECEQA
Decrement and Set T If Equal Zero
DECEQA
(AGU)
Description
Status and Conditions that Affect Instruction
None.
Status and Conditions Changed by Instruction
Example
deceqa r0
Instruction Formats and Opcodes
Instruction Fields
Rx RRRR AGU Source/Destination Register
Operation Assembler Syntax
Rx – 1
→ Rx; if Rx==0, then 1 → T, else 0 → T
DECEQA Rx
DECEQA Rx
Decrements an AGU register (Rx) and sets the T bit if the result is zero. SP cannot be used as an operand of
this instruction.
Register Address Bit Name Description
SR[1] T Set if result = 0, cleared otherwise.
Register/Memory Address Before After
R0 $0000 0001 $0000 0000
SR $00E4 0000 $00E4 0002
Instruction Words Cycles Type Opcode
15 8 7 0
DECEQA Rx 1 1 2 1 1 1 0 R R R R 1 1 1 1 0 1 1 0
0000 N0 0100 — 1000 R0 1100 R4
0001 N1 0101 — 1001 R1 1101 R5
0010 N2 0110 — 1010 R2 1110 R6
0011 N3 0111 SP 1011 R3 1111 R7
Note: This instruction can specify R8-R15 as operands by using a high register prefix. SP cannot be
used as an operand for this instruction.