Freescale Semiconductor StarCore SC140 - Manual (Page 703)

SUB
SC140 DSP Core Reference Manual A-389
SUB
Subtract (DALU)
SUB
Description
Status and Conditions that Affect Instruction
Status and Conditions Changed by Instruction
Example 1
sub d1,d0,d2
Operation Assembler Syntax
Dn – #u5
→ Dn
SUB #u5,Dn {0
≤ u5 < 32}
Db – Da
→ Dn
SUB Da,Db,Dn
SUB #u5,Dn
Subtracts an immediate unsigned 5-bit value from a data register (Dn) and stores the result in the
destination data register (Dn).
SUB Da,Db,Dn
Subtracts one source data register (Da) from a second data register (Db) and stores the result in a
destination data register (Dn).
Register Address Bit Name Description
SR[2] SM If set, selects 32-bit arithmetic saturation mode.
SR[5:4] S[1:0] Scaling mode bits determine which bits in the result are used in the
Ln bit calculation.
Register Address Bit Name Description
SR[0] C Calculates the borrow and updates the carry bit in the status
register.
EMR[2] DOVF Set if the result cannot be represented in 40 bits, or if the result
saturates to 32 bits in arithmetic saturation mode.
Ln L If not in arithmetic saturation mode (SR [SM] = 0), calculates and
updates the Ln bit in the destination register. If in arithmetic
saturation mode (SR [SM] = 1), clears the Ln bit in the destination
register.
Register/Memory Address Before After
D0 $00 0000 0005
D1 $00 0000 0008
SR $00E4 0000 $00E4 0001