Freescale Semiconductor StarCore SC140 - Manual (Page 384)

A-70 SC140 DSP Core Reference Manual
BMCHG.W
Status and Conditions Changed by Instruction
Example
bmchg #$f0f0,d1.h
Instruction Formats and Opcodes
Instruction Fields
C1 CCC Control Registers
DR HHHH Data/Address Register
Register Address Bit Name Description
Ln L Clears the Ln bit in the destination data register.
Register/Memory Address Before After
immediate $F0F00000
L1:D1 $0:$FFF0F07B22 $0:$FF00007B22
Instruction Words Cycles Type Opcode
15 8 7 0
BMCHG #u16,C1.H 2 2 3 0 0 0 1 0 0 1 0 i i i 1 0 C C C
1 0 1 i i i i i i i i i i i i i
15 8 7 0
BMCHG #u16,C1.L 2 2 3 0 0 0 1 0 0 1 0 i i i 0 0 C C C
1 0 1 i i i i i i i i i i i i i
15 8 7 0
BMCHG #u16,DR.H 2 2 3 0 0 0 0 1 0 1 0 i i i 1 H H H H
1 0 1 i i i i i i i i i i i i i
15 8 7 0
BMCHG #u16,DR.L 2 2 3 0 0 0 0 1 0 1 0 i i i 0 H H H H
1 0 1 i i i i i i i i i i i i i
000 EMR 010 - 100 — 110 —
001 VBA 011 - 101 SR 111 MCTL
0000 D0 0100 D4 1000 R0 1100 R4
0001 D1 0101 D5 1001 R1 1101 R5
0010 D2 0110 D6 1010 R2 1110 R6
0011 D3 0111 D7 1011 R3 1111 R7
Note: If registers D8–D15 or R8–R15 are accessed instead of D0–D7 or R0–R7, a prefix is used.