Freescale Semiconductor StarCore SC140 - Manual (Page 215)

Stack Support
SC140 DSP Core Reference Manual 5-35
Table 5-13 describes the stack memory map while performing a single or a dual push access.
Up to two pop instructions are supported in a single execution set. If two pop instructions are included in a
single execution set, one pop instruction must use an even register operand and the other pop instruction
must use an odd register operand.
An execution set that includes one or two pop instructions restores De from SP–8 and/or Do from SP–4
(See Table 5-12 for the definition of De and Do). The execution set decrements the original stack pointer
by eight as specified by the operands. Note that if the stack is popped with one register only, the data from
the other pushed register may be lost.
Pushing and popping the data extension register (Dx.e + Lx tag bit) are unique operations. It is possible to
push two extensions that are coupled together to form a single operand, or to push a single extension. The
single extensions are divided between the even and odd tables. In both cases, the push operation occupies
32 bits. For more information, see Table 5-12, as well as the PUSH and POP instructions in Appendix A.
For correct operation, the stack should be popped in reverse order with exactly the same register pairing as
it was pushed. When dual push instructions are used in an execution set, the corresponding pop instructions
should be dual. The pop operands should match the corresponding push operands.
In addition to the push and pop instructions, the stack can be accessed directly with move or bit-mask
instructions. The available addressing modes are shown in Table 5-14. The two addressing modes differ in
the instruction word count. Note that the user cannot use addressing modes that update SP during the
access, but only short or word displacement addressing modes that leave the SP unchanged.
5.5.4 Shadow Stack Pointer Registers
The stack normally grows by incrementing SP and shrinks by decrementing SP. Both stack pointers have
shadow registers that contain a decremented value of the stack pointers. When the shadow register is not
valid, the pop instruction is executed in two cycles where the first cycle is used to decrement the stack
pointer. When the shadow register is valid, the pop instruction is executed in only one cycle.
When an NSP or ESP is written (by TFRA), then its shadow register automatically becomes invalid. In this
situation, the first pop instruction takes an additional cycle. When a push/pop instruction is executed, then
the shadow register of the active NSP or ESP becomes valid.
Table 5-13. Stack Memory Map
Type Memory Location X+4 Memory Location X
Single push - even register Unused Even operand
Single push - odd register Odd operand Unused
Dual push Odd operand Even operand
Table 5-14. Stack Move Instructions
Addressing Mode Description
(SP - xx) Subtract offset by a shifted unsigned 5-bit or
6-bit immediate value. The SP remains
unchanged.
(SP + xxxx) Add a signed 15-bit immediate offset. The SP
remains unchanged.