Freescale Semiconductor StarCore SC140 - Manual (Page 71)

Address Generation Unit
SC140 DSP Core Reference Manual 2-39
• Post-decrement, (Rn)- —The operand address is in the address register. After the operand address
is used, it is decremented by the access width (1, 2, 4, or 8 bytes) and stored in the same address
register. The type of arithmetic used for updating R0-R7 is determined by programming the
MCTL register. An example is: move.l (r3)-,d2. In this case, the value in r3 is decremented
by four after the move has taken place.
• Post-increment by Offset Ni, (Rn) + Ni — The operand address is in the address register. After the
operand address is used, it is incremented or decremented by an amount determined by the signed
contents of the Ni register pre-shifted to the left by 0, 1, 2, or 3 bits according to the access width.
The result is stored in the same address register. The type of arithmetic used for updating R0-R7 is
determined by programming the MCTL register. The contents of the Ni register are unchanged. An
example is: move.w d3,(r2)+n3. The access width is two, so the increment is twice the value
in the n3 register.
• Indexed By Offset N0, (Rn + N0) — The operand address is the sum of the contents of the address
register and the signed contents of the N0 register, pre-shifted to the left by 0, 1, 2, or 3 bits according
to the access width. The type of arithmetic used for updating R0-R7 is determined by programming
the MCTL register. The contents of the Rn and N0 registers are unchanged. For example:
move.b
d6,(r3+n0) . The access width is one, so the contents of the n0 register are used
directly to modify the address before the move is done.
Note that only the N0 offset register can be used in this addressing mode.
• Indexed by Address Register Rm, (Rn + Rm) — The operand address is the sum of the contents
of the address register Rn and the contents of the address register Rm, pre-shifted to the left by 0, 1,
2, or 3 bits according to the access width. The type of arithmetic used for updating R0-R7 is
determined by programming the MCTL register. The contents of the Rn and Rm registers are
unchanged. An example is: move.l (r0+r2),d6. Here, the access width is four, so the value in
r2 is shifted left two bits before adding to the address in r0.
Note that only address registers (R0–R7) can be used as Rm.
• Short Displacement, (Rn + x) — The operand address is the sum of the contents of the address
register Rn and a short displacement x that occupies three bits in the instruction word. The
displacement (unsigned) is first shifted to the left by 0, 1, 2, or 3 bits according to the access width.
It is then zero-extended to 32 bits and added to Rn to obtain the operand address. Thus, the
displacement can range from [0] to [+7] bytes, words, long words, or two long words according to
the access width. The contents of the Rn register are unchanged. The type of arithmetic used for
updating R0-R7 is determined by programming the MCTL register. An example is: move.l
d4,(r3+$1c)
. The access width is four, and the displacement encoded in the instruction is seven
(4 x 7 = 28 = $1c).
• Word Displacement, (Rn + xxxx) — The operand address is the sum of the contents of the address
register Rn and an immediate displacement. The displacement is a signed 15-bit word that requires
a second instruction word. It is sign-extended to 32 bits and then added to Rn to obtain the operand
address. Thus, the displacement can range from [-16,384] to [+16,383] bytes, [-8192] to [+8191]
words, [-4096] to [+4095] long words, or [-2048] to [+2047] two long words according to the access
width. The contents of the Rn register are unchanged. The type of arithmetic used for updating
R0-R7 is determined by programming the MCTL register.
• SP Short Displacement, (SP – xx) — The instruction word contains a 5-bit or 6-bit short unsigned
immediate index field. This field is first shifted to the left by 1 or 2 bits according to the access width,
then zero-extended to form a 32-bit offset and subtracted from the active stack pointer (NSP in
Normal mode, ESP in Exception mode) to obtain the operand address. Thus, the displacement can
range from [0] to [31/63] words or long words according to the access width. The contents of the