Freescale Semiconductor StarCore SC140 - Manual (Page 110)

3-10 SC140 DSP Core Reference Manual
PLL and Clock Registers
3.1.2.1 Clearing EMR Bits
The ILIN, ILST, DOVF, and NMID bits can only be set by the hardware. These events should be regarded
as asynchronous to the program flow given the complex relationship between the events that set these bits
and the program flow. These bits are typically cleared by the SW during an exception service routine.
DOVF can be cleared outside of an exception service routine for polling usage.
As a programming guideline, the EMR bits should be cleared with great care, to ensure that no information
about new events is lost. An EMR bit is cleared by writing back 1 to it using the BMCLR instruction
typically inside an exception service routine. Example 3-1 illustrates the use of the BMCLR instruction in
the interrupt service routine of an overflow exception, which is activated when DOVF is set.
Example 3-1. Clearing an EMR Bit
BMCLR #$fffb,EMR.L
This instruction writes back a zero to every bit in EMR.L except for DOVF, which is written with the same
value it contained when it was read. Because DOVF was set to begin with, it is now cleared. Other bits set
in EMR.L are not affected. Due to this special behavior, the EMR should not be stored to the stack during
a context switch. This ensures that no bits are cleared unintentionally when the EMR is restored.
3.2 PLL and Clock Registers
The SC140 core provides a programming interface to an on-chip phase-locked loop (PLL). The core has
two registers that control settings for the PLL as well as clocks, named PCTL0 and PCTL1. The definition
and usage of these registers is chip specific. In systems where the PLL is controlled without these registers,
they cannot be used as general purpose registers.