Freescale Semiconductor StarCore SC140 - Manual (Page 225)

Processing States
SC140 DSP Core Reference Manual 5-45
Table 5-18. Exit Wait Processing State due to an Interrupt or NMI
5.7.7 Stop Processing State
The stop processing state is the lowest power consumption state and is entered by the execution of the
STOP instruction. After the STOP instruction has been issued, it takes a system-specific number of clock
cycles to enter the stop state and turn off the global clocks to the entire core and peripherals. The core exits
from the stop processing state when one of the following occurs:
• A dedicated core “wake from stop” input signal is asserted.
• The RESET signal is asserted.
• The JTAG controller issues a debug request.
• The EE0 signal (programmed as a debug request input) is asserted.
Debug request from the EOnCE may also exit from Stop Processing State, if it occurs few cycles after the
STOP instruction execution (exact time may vary according to the specific clock scheme implemented).
If an exit from the stop processing state is caused by assertion of the EE0 signal or a debug request, the
core either enters the debug state immediately, or the debug exception is serviced according to the EOnCE
configuration.Refer to the EOnCE Reference Manual, for further details.
If the Stop Processing State is exited by assertion of the RESET signal, the core enters the reset processing
state.
If the stop processing state is exited during the assertion of an external interrupt request, the core enters the
exception mode and services the highest priority pending interrupt. If no interrupt is pending, the core
enters the execution state and executes the instruction following the STOP instruction that caused the entry
into the stop state.
Interrupt Request
Disable Interrupts
(DI)
Disable NMI
(NMID)
Wait Process
Maskable Request with IPL > core IPL
as determined by the I2–I0 bits of the
SR
Clear (interrupts
enabled)
Clear or set Exit the wait processing state.
Jump to the Interrupt Service
Routine (ISR).
Maskable Request with IPL > core IPL
as determined by the I2–I0 bits of the
SR
Set (interrupts
disabled)
Clear or set Exit the wait processing state.
Enter execution state and
continue program execution,
following the WAIT instruction.
No jump to the ISR.
Maskable Request with IPL <= core IPL
as determined by the I2–I0 bits of the
SR
Clear or set Clear or set Remain in the wait processing
state.
Non-maskable request Clear or set Clear Exit the wait processing state.
Jump to the ISR.
Non-maskable request Clear or set Set Exit the wait processing state.
Enter execution state and
continue program execution,
following the WAIT instruction.
No jump to the ISR.