Freescale Semiconductor StarCore SC140 User Manual
Page 65
Address Generation Unit
SC140 DSP Core Reference Manual
2-33
During every instruction cycle, the two AAUs can generate one 32-bit program memory address on the
PAB (in case of change of flow) or two 32-bit data memory addresses (one on each of the XABA and
XABB). Each AAU can generate an address to access a byte, a 16-bit word, a 32-bit long word, or a 64-bit
two-word long operand in memory to feed into the DALU in a single cycle.
Each AAU can update one address register during one instruction cycle. The modifier control register
(MCTL) specifies the type of arithmetic to be used in the address register update calculation. The address
arithmetic instructions provide arithmetic operations for address calculations or for general purpose
calculations.
The two AAUs are identical. Each contains a 32-bit full adder, called an offset adder, which can perform
the following:
•
Add or subtract two AGU registers
•
Add an immediate value
•
Increment or decrement an AGU register
•
Add the PC
•
Add with reverse-carry
The offset adder can also perform compare or test operations as well as arithmetic and logical shifts. The
offset values added in this adder can be pre-shifted left by 1, 2, or 3 bits according to the access width. In
reverse-carry mode, the carry propagates in the opposite direction.
A second full adder, called a modulo adder, adds the summed result of the first full adder to a modulo
value, M or minus M, where M is stored in the selected modifier register. In modulo mode, a modulo
comparator tests whether the result is inside the buffer by comparing the results to the B register, choosing
the correct result from the offset adder or the modulo adder.
Section 2.3.5, “Arithmetic Instructions on Address Registers.”