Freescale Semiconductor StarCore SC140 - Manual (Page 354)

A-40 SC140 DSP Core Reference Manual
AND
AND
Bitwise AND (DALU)
AND
Description
These operations perform a "logical and" between the two source operands, and store the result in the
destination operand.
Status and Conditions that Affect Instruction
None.
Operation Assembler Syntax
#0u16
• Da → Dn
AND #0{u16},Da,Dn {0
≤ u16 < 2 16
}
#u16$0000
• Da → Dn
AND #{u16}$0000,Da,Dn {0
≤ u16 < 2 16
}
Da
• Dn → Dn
AND Da,Dn
AND #0{u16},Da,Dn
The immediate unsigned word is zero-extended in bits [40:16] to form a 40-bit immediate operand. This
operand is then ANDed with the contents of a source data register (Da), and the result stored in a
destination data register (Dn). The HP and extension (bits [40:16]) of the destination register are cleared as
a result of this instruction.
The { } are not part of the assembler syntax, they are used here for clarity. For example, given an
immediate value of $27A6, using D0 as the source data register, and using D1 as the destination data
register, this instruction would be written as:
and #$027a6,d0,d1
AND #{u16}$0000,Da,Dn
A 40-bit operand is formed with zeros in bits [15:0], the immediate word in bits [31:16], and bit 31 copied
to bits [39:32] (sign-extended). This operand is then ANDed with the contents of a source data register
(Da), and the result stored in a destination data register (Dn). The LP of the destination register is cleared
as a result of this instruction.
The { } are not part of the assembler syntax, they are used here for clarity. For example, given an
immediate value of $27A6, using D0 as the source data register, and using D1 as the destination data
register, this instruction would be written as:
and #$27a60000,d0,d1
AND Da,Dn
Performs a bitwise AND on the contents of two source data registers (Da, Dn) and stores the result in the
destination (second) data register (Dn).