Freescale Semiconductor StarCore SC140 - Manual (Page 674)

A-360 SC140 DSP Core Reference Manual
RND
Status and Conditions that Affect Instruction
Status and Conditions Changed by Instruction
Example 1
rnd d1,d5
Example 2
rnd d2,d1
$CAFE 40001100 1010 1111 1110 0100 0000 0000 0000
After rounding $CAFE 80001100 1010 1111 1110 1000 0000 0000 0000
Scaling up is selected in SR[4-5], and 2’s complement rounding is selected in SR[3]. Bit 15 is rounded up
because bit 14 = 1.
Register Address Bit Name Description
SR[2] SM If set, selects 32-bit arithmetic saturation mode.
SR[3] RM Rounding mode
SR[5:4] S[1:0] Scaling bits determine which bits in the result are used in the Ln bit
calculation and which bits are used in rounding.
Register Address Bit Name Description
Ln L If not in arithmetic saturation mode (SR [SM] = 0), calculates and updates
the Ln bit in the destination register. If in arithmetic saturation mode (SR
[SM] = 1), clears the Ln bit in the destination register.
EMR[2] DOVF Set if the result is not representable in 40 bits, or if the result saturates to
32 bits in saturation mode.
Register/Memory Address Before After
SR $00E0 0000
D1 $00 0000 FFFF
L5:D5 $0:$00 0001 0000
EMR $0000 0000
Register/Memory Address Before After
SR $00E0 0028
D2 $00 CAFE 4000
L1:D1 $0:$00 CAFE 8000
EMR $0000 0000