Freescale Semiconductor StarCore SC140 - Manual (Page 346)

A-32 SC140 DSP Core Reference Manual
ADDL1A
ADDL1A
Add With One-Bit Arithmetic Shift Left
ADDL1A
of Source Operand (AGU)
Description
Status and Conditions that Affect Instruction
Example
addl1a r0,r1
In binary:
Operation Assembler Syntax
(rx<<1) + Rx
→ Rx
ADDL1A rx,Rx
ADDL1A rx,Rx
Performs a one-bit arithmetic shift left on the data from source AGU register (rx) and adds the result to a
second source AGU register (Rx). The sum is stored back in Rx. For R0-R7 destinations, the operation is
affected by the modifier mode selected in MCTL.
Register Address Bit Name Description
SR[18] EXP Determines which stack pointer is used when the stack pointer is an
operand. Otherwise, the instruction is not affected by SR.
MCTL[31:0] AM3–AM0 Address modification bits when updating R0–R7. Otherwise, the
instruction is not affected by MCTL.
Register/Memory Address Before After
MCTL $0000 0000
R0 $0000 0055
R1 $0000 0011 $0000 00BB
R0 0101 0101
R0 shifted left 1010 1010
R1 0001 0001
Sum 1011 1011