Freescale Semiconductor StarCore SC140 - Manual (Page 25)

SC140 DSP Core Reference Manual xxv
ISR Interrupt service routine
JTAG Joint test action group
LA Last address
LCn Loop counter register n
Ln Limit tag bit n
LP Low portion of a data register
LSB Least significant bits
LSP Least significant portion
Mn AGU modifier register
MAC Multiply-accumulate
MCTL Modifier control register
MIPS Million instructions per second
MMACS Million multiply and accumulate operations per second
MSB Most significant bits
MSP Most significant portion
Nn AGU offset register n
NMI Non-maskable interrupt
NSP Normal mode stack pointer
OS Operating system
PAB Program address bus
PAG Program address generator
PC Program counter register
PCU Program control unit
PDB Program data bus
PDU Program dispatch unit
PIC Programmable interrupt controller
PLL Phase locked loop
PSEQ Program sequencer unit
Rn AGU address register n
Table 1. Abbreviations (Continued)
Abbreviation Description