Example – Freescale Semiconductor StarCore SC140 User Manual
Page 738
A-424
SC140 DSP Core Reference Manual
VSL
Status and Conditions that Affect Instruction
Status and Conditions Changed by Instruction
None.
Example
vsl.2w d1:d3,(r0)+n0
Register Address
Bit Name
Description
MCTL[31:0]
AM3–AM0
Address modification bits for R0–R7.
SR[8]
VF0
Viterbi flag 0 set by MAX2VIT D4,D2.
SR[9]
VF1
Viterbi flag 1 set by MAX2VIT D4,D2.
SR[10]
VF2
Viterbi flag 2 set by MAX2VIT D0,D6.
SR[11]
VF3
Viterbi flag 3 set by MAX2VIT D0,D6.
EMR[16]
BEM
Set if big endian mode, cleared if little endian mode.
Register/Memory Address
Before
After (Little Endian)
After (Big Endian)
MCTL
$0000 0000
SR
$00e4 0000
D1
$00 2A62 EA79
D3
$00 5437 9EAC
N0
$0000 0002
R0
$0000 0060
$0000 0068
$0000 0068
$0060
$D4F2
$D4F3
$0062
$D4F3
$D4F2