Freescale Semiconductor StarCore SC140 - Manual (Page 726)

A-412 SC140 DSP Core Reference Manual
TRAP
TRAP
Execute a Software Exception (AGU)
TRAP
Description
TRAP
The starting address of the exception processing routine is VBA[31:12]:$000.
Status and Conditions that Affect Instruction
None.
Operation Assembler Syntax
Next PC
→ (ESP), SR → (ESP + 4),
ESP + 8
→ ESP
VBA[31:12]:trap_vector
→ PC
0
→ EXP
0
→ C
0
→ T
00
→ S[1:0]
0
→ SLF
0000
→ LS[3:0]
TRAP {trap_vector = $000}
TRAPn
The TRAP instruction creates a precise software interrupt, halting execution and jumping to a code section
pointed to from the exception table. The term precise is defined such that the exception timing is
guaranteed to be synchronous with the instruction execution. The TRAP exception occurs immediately
after the TRAP instruction. The current state of the machine is saved by pushing the values of the SR and
the next PC onto the exception stack with two simultaneous 32-bit long-word memory accesses. The SR
bits listed below are then set or cleared, including setting the interrupt priority level to the highest value
(masking all maskable interrupts). The starting address of the exception processing routine is loaded to the
PC and the Exception working mode is entered.