Macsu, Fractional multiply-accumulate, Operation assembler syntax – Freescale Semiconductor StarCore SC140 User Manual
Page 553
MACSU
SC140 DSP Core Reference Manual
A-239
MACSU
Fractional Multiply-Accumulate
MACSU
Signed By Unsigned (DALU)
Description
Status and Conditions that Affect Instruction
None.
Status and Conditions Changed by Instruction
Example
macsu d0,d1,d4
Operation
Assembler Syntax
Dn + (Dc.H * Dd.L)
→ Dn
MACSU Dc,Dd,Dn
MACSU Dc,Dd,Dn
Performs signed fractional multiplication of the signed 16-bit HP of one data register (Dc) in a register pair
(Dc and Dd) by the unsigned 16-bit LP of the other data register (Dd). It then adds the sign-extended 32-bit
product to a destination data register (Dn).
Register Address
Bit Name
Description
Ln
L
Clears the Ln bit in the destination register.
EMR[2]
DOVF
Set if the result cannot be represented in 40 bits.
Register/Memory Address
Before
After
D0
$FF C000 0000
D1
$00 0000 0001
L4:D4
$0:$00 0000 0000
$0:$FF FFFF 8000
EMR
$0000 0000