Freescale Semiconductor StarCore SC140 - Manual (Page 371)

ASR
SC140 DSP Core Reference Manual A-57
ASR
Arithmetic Shift Right
ASR
By One Bit (DALU)
Description
Status and Conditions that Affect Instruction
Status and Conditions Changed by Instruction
Example
asr d5,d3
Operation Assembler Syntax
Da>>1
→ Dn
ASR Da,Dn
ASR Da,Dn
Performs an arithmetic right shift by one bit on the source register Da, and stores it in the destination
register Dn. The LSB (bit 0) of the source register is copied into the status register carry (C) bit. Bits [39:1]
of the source register are copied into bits [38:0] of the destination register. Bit 39 of the source register is
copied into bit 39 of the destination register.
Register Address Bit Name Description
SR[2] SM If set, selects 32-bit arithmetic saturation mode.
SR[5:4] S[1:0] Scaling mode bits determine which bits in the result are used in the
Ln bit calculation.
Register Address Bit Name Description
SR[0] C Da[0] is stored in the carry bit.
Ln L If not in arithmetic saturation mode (SR [SM] = 0), calculates and
updates the Ln bit in the destination register. If in arithmetic
saturation mode (SR [SM] = 1), clears the Ln bit in the destination
register.
EMR[2] DOVF Set if the result cannot be represented in 40 bits, or if the result
saturates to 32 bits in arithmetic saturation mode.
Register/Memory Address Before After
D5 $00 0000 7903
L3:D3 $0:$00 0000 3C81
0 15 16 31 32 39 C 39