Freescale Semiconductor StarCore SC140 - Manual (Page 702)

A-388 SC140 DSP Core Reference Manual
STOP
STOP
Stop Instruction Processing (AGU)
STOP
Description
Status and Conditions that Affect Instruction
Status and Conditions Changed by Instruction
None
Instruction Formats and Opcodes
Operation Assembler Syntax
Enter the stop processing state. STOP
STOP
Halts instruction execution and enters the STOP processing state. This state is intended for the lowest
power consumption mode. The core informs the system about the intention to enter the STOP processing
state, and it is up to the system to shut down the clocks.
All activity in the processor is halted until one of the following actions occurs:
• The wake_from_stop signal is asserted. In many chip configurations, this core interface signal is
connected to one of the external interrupt request pins.
• A low level is applied to the RESET_B signal.
• A low level is applied to the EE0 debug signal.
• A JTAG debug request command is made.
Any of these actions causes the core to exit the STOP processing state, as follows:
If STOP is exited by assertion of the RESET signal, the processor enters the reset processing state.
If STOP is exited in parallel with an external interrupt request, the processor services the highest priority
pending interrupt. If no interrupt is pending, or if no interrupt is enabled, the processor resumes execution
at the instruction following the STOP instruction that caused entry into the stop state.
If STOP is exited by a low level on the EE0 signal or a JTAG debug request command, the processor enters
the debug state immediately.
Register Address Bit Name Description
SR[18] EXP Determines execution working mode.
Instruction Words Cycles Type Opcode
15 8 7 0
STOP 1 8 4 1 0 0 1 1 1 1 1 0 1 1 1 1 0 0 1